In many high-speed data applications, a clock edge is employed to capture or propagate data. Clock jitter is a deviation from an ideal timing of clock transition events, such as a rising or falling clock edge. Cycle-to-cycle jitter is a type of jitter that corresponds to variations in the period of a clock signal. The cycle-to-cycle jitter of a clock cycle can result in variations (e.g., a reduction) in the clock period or a decrease in frequency over time. Jitter can result from many sources, the dominant ones being supply noise in the distribution and cross-coupling from interconnect in the on-chip distribution. As an example, Delay locked loops (DLL's) and other circuitry can be employed to generate clock signals. A DLL as well as other associated circuitry can introduce cycle-to-cycle jitter into the clock signal. The jitter in the clock signal can decrease the available frequency and otherwise degrade performance by circuitry that is controlled by the jittering clock.